#riscv

Build the OpenSBI firmware and U-Boot for RISC-V from source, then boot a kernel through the full chain in QEMU. The addresses explained.

Xen Summit 2026 in Munich: three Vates talks, a RISC-V port that went from QEMU to real boards, and a hallway track at least as good as the talks.

Thân máy nhôm mỏng nhẹ không quạt tản nhiệt của MacBook Air cho cảm giác cơ động cao, nhưng khi ném...

NetBSD 11.0 boots a virtual machine in about 10 ms with its new MICROVM kernel. It is also the first stable release to run on 64-bit RISC-V boards.

Did you ever think about how your CPU executes the code that you wrote?

Arduboy's CHGame Rev0 is a $39 bare-board handheld: 48 MHz RISC-V, a 128x128 color LCD, and every GPIO pin broken out for hacking.

We have been building RISC-V cores, IP, VIP, accelerators and SoC reference designs. For WZ-HFT, we...

Cài đặt GCC cross-compiler và QEMU User Emulation Chạy compile trực tiếp trên bo mạch...

Linux 7.3 turns on AF_ALG restriction by default, Intel proposes DRM Fabric for accelerators, and YOLOX runs on the open Etnaviv NPU stack.

RISC-V will eventually own the cheap-as-dirt single-use microcontroller space. Not due to its ISA...

WCH's CH32V407 Brings Vector: A 200MHz RISC-V microcontroller with vector extensions, 8MB of optional PSRAM, and a $2.40 price tag. Here is what the CH32V407 can actually do.

Originally published at norvik.tech Introduction Dive deep into RISC-V architecture,...