#fpga

Adiuvo Explorer Board 99: The open-source Adiuvo Explorer Board puts an AMD Artix UltraScale+ FPGA in reach for $99 — USB-C powered, Pmod-ready, and built for makers.

50 Forgix Puts Raspberry: Adiuvo's $50 Forgix drops a Raspberry Pi RP2354 and an Efinix FPGA onto one breadboard-friendly board, with an open-source bitstream loader.

I've built the KAN FPGA Accelerator Proxy. It's a Python-based proxy tool designed to simulate the...

v0.8 (2026-06-03) Engineering retry of v0.5 Phase 4 Belnap AND/OR on IBM Heron r2 via K-map / Quine-McCluskey minimum-SOP Boolean simplification + inclusion-exclusion XOR layering. ibm_kingston Job d8fr2jo7jphs739mn2d0, 22.2 sec wall-clock: **32/32 PASS** (v0.5: 18/32, 56.2%) at avg fidelity **0.7302** (v0.5: 0.3182, +41.20 pp). Avg post-transpile depth **422** (v0.5: 2443, -83%). AND vs OR fidelity gap 0.75 → **0.03 (symmetric)** — v0.5 finding F9 relaxation-bias hypothesis confirmed engineering-correctable rather than intrinsic. Companion in Paper 162 §6.0g sub-result A: Sampler-level XX Dynamical Decoupling re-run of Paper 162 §6.0e 8-bit decoder on ibm_marrakesh (Job d8fr243o3njc73f0nnf0), honest NEGATIVE finding F10: DD lowered fidelity 49.12% → 26.25% (-22.87 pp) on 184-CZ MCX-heavy circuit; 8/8 correct-top-outcome preserved. Combined honest reading: depth reduction (QM, B1) is the effective lever on Heron r2 for these gate families; pulse-level error mitigation (naive XX DD, A) is not. Honest scope: engineering retry, NOT paradigm claim, NOT quantum advantage, NOT new D-FUMT-8 op. Belnap subset (bit 2 = 0) unchanged from v0.5. 4-substrate framing from v0.7 preserved. Zenodo DOI 10.5281/zenodo.20521157 (v0.8, new-version of v0.7 / 20192813; concept DOI lineage maintained across v0.3 / v0.6 / v0.7 / v0.8). Public companion: https://note.com/nifty_godwit2635/n/naa5022b7f014 (note.com, 藤本伸樹, 2026-06-03 14:24 JST). Three-party co-authorship per OUKC charter v1.0.

The $199 ModRetro M64 uses AMD FPGA hardware to play original N64 carts, betting accuracy and HDMI can win retro fans.

SMGP: Building an AI That Actually Remembers What You Told It I spent a few months...

v0.6 (2026-05-10) FOUR-substrate cross-verification of an 8-valued (D-FUMT-8) ALU including a SELF-reflexive primitive. Zenodo v0.6 DOI 10.5281/zenodo.20101174 (parent v0.3 DOI 10.5281/zenodo.20091185, concept DOI lineage). Substrates: (1) Verilog FPGA on TWO Sipeed silicon families — Tang Console 138K (GW5AST-138B LittleBee5 A, User Code 0x00005C27) + Tang Nano 9K (GW1NR-9C LittleBee1 C IDCODE 0x1100481B, User Code 0x00001D46), running BYTE-FOR-BYTE same 138-line dfumt8_alu_synth.v Verilog with bit-identical 0 changes to ALU logic. (2) Qiskit Aer simulator — Phase 1-5 cumulative 231/231 truth-table entries. (3) IBM Heron r2 real quantum hardware — Phase 1+2+3+5 cumulative 144/144 entries with avg fidelity 0.954. NEW v0.6 finding F10: chip-portability evidence — synthesis bug or vendor-specific assumption would diverge between LittleBee5 (5nm-class) and LittleBee1 (28nm-class) Gowin architectures; absence of divergence is operational evidence. v0.5 corrigendum (Tang Nano 9K = computational evidence only) RESOLVED via STEPs 1038/1039 with authentic Sipeed Tang Nano 9K (秋月電子 g117448, ¥2,980). Reproducibility entry-cost lowered to ~$20. Lean 4 refinement proof (292 LOC, 0 sorry). Honest scope: NOT first 8-valued quantum (Shi et al. MIT 2026 d=8 trapped-ion Grover prior); novel quadruple is (D1) specific Belnap+ontological 8-tuple, (D2) SELF-reflexive primitive as hardware fixed point, (D3) four-substrate cross-verification bound to Lean 4, (D4 NEW v0.6) chip-portability across two Gowin silicon architectures. Three-party co-authorship per OUKC charter v1.0.

v0.3 (2026-05-09) three-substrate cross-verification of an 8-valued (D-FUMT-8) ALU including a SELF-reflexive primitive. Substrates: (1) Verilog FPGA — Tang Nano 9K 37 LUT4 + Tang Console NEO Phase 2C/3 silicon SRAM-programmed (User Codes 0x000084BA + 0x00005C27). (2) Qiskit Aer simulator — Phase 1-5 cumulative 231/231 truth-table entries. (3) IBM Heron r2 real quantum hardware — Phase 1+2 cumulative 96/96 entries with avg fidelity 0.953. Lean 4 refinement proof (292 LOC, 0 sorry). Honest scope: NOT first 8-valued quantum (Shi et al. MIT 2026 d=8 trapped-ion Grover prior); novel triple is (D1) specific Belnap+ontological 8-tuple, (D2) SELF-reflexive primitive as hardware fixed point, (D3) three-substrate cross-verification bound to Lean 4. Zenodo DOI 10.5281/zenodo.20091185. Three-party co-authorship per OUKC charter v1.0.

Originally published on the Sienovo Engineering Blog. Sienovo is the overseas brand of 深圳信迈 (Shenzhen...

This post is the first in a series on FPGA development with open-source tools. By the end you will...

CERN's Large Hadron Collider generates 40 million bunch crossings per second. Only AI models running on FPGAs at 100-nanosecond inference speeds can decide what's worth keeping — and an open-source tool called hls4ml makes it possible.

1) what “pause” means in an FPGA digital clock A typical FPGA digital clock has at least two...